• COSMOS: a compositional design-space exploration methodology for hardware accelerators

    Our paper "COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators" has been published in ACM Transactions on Embedded Computing Systems (TECS). The paper is available here. The paper has been presented at the ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). The slides of the presentation are available here.

    The paper describes COSMOS, an automatic methodology for the design-space exploration of complex hardware accelerators. COSMOS coordinates both high-level synthesis and memory optimization tools in a compositional way. Thanks to the co-design of datapath and memory, COSMOS produces a large set of Pareto-optimal implementations for each component of a given accelerator. Additionally, COSMOS leverages compositional design techniques to quickly converge to the desired trade-off point between cost and performance for the entire accelerator architecture.

  • In the News: Prof. Carloni interviewed on the coming engineering renaissance in chip design

    Luca Carloni gave an interview on the future of chip design and how his own research and teaching hope to contribute to the coming renaissance. Access here the full interview.

  • In the News: Our ongoing work on Brain-Computer Interfaces

    Our group is a member of a research team led by Prof. Ken Shepard working on Brain-Computer Interfaces. This work, funded by DARPA under the NESD program, was recently highlighted in Columbia Engineering's website. Access the news story here.

  • Congratulations to Paolo for defending his thesis!

    Today Paolo successfully defended his thesis, titled "Scalable System-on-Chip Design". Congratulations, Dr. Mantovani!

  • Congratulations to Young Jin for defending his thesis!

    Today Young Jin successfully defended his thesis, titled "Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip". Congratulations, Dr. Yoon!

  • Prof. Carloni named IEEE Fellow

    Luca Carloni has been named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for "contributions to system-on-chip design automation and latency-insensitive design".

    Extraordinary record of accomplishments is required to reach the highest grade of IEEE membership. More information on Prof. Carloni's nomination and many professional achievements can be found in an article that made the headlines of the Computer Science webpage.

  • Our paper on parallelizing QEMU to appear at CGO'17

    Our paper "Cross-ISA Machine Emulation for Multicores" has been accepted for publication at the upcoming CGO'17 conference to be held in Austin, TX. The work described in the paper enables parallel execution of parallel cross-ISA workloads in QEMU. That is, multi-core hosts can be exploited to speed up the emulation of guests that are (1) multi-core systems or (2) multi-threaded user-mode programs.

    Code changes resulting from this work have started making their way to upstream QEMU. In particular, QEMU v2.7 includes (1) our improved hashing for the TB block hash table and (2) the implementation and use of QHT for scalable TB lookups (commit, commit); see the merge commit. Moreover, the following code has been merged for inclusion in the upcoming QEMU v2.8: (1) the use of the host's atomic instructions to emulate the guest's atomics (x86, arm, aarch64; merge commit), and (2) the necessary work to safely support multi-threaded execution (commit, commit; merge commit).

    This work would not have been possible without the QEMU community. In particular, Paolo Bonzini and Alex Bennée have made key contributions and are coauthors of the paper. Other QEMU developers such as Sergey Fedorov and Richard Henderson have been actively involved by writing code as well as making significant improvements to our ideas and code. We are very grateful for their help and their patience with us.

  • Two SLD papers presented at DAC'16

    Two papers coauthored by SLD members have been presented in June at DAC 2016 in Austin, TX.

    Paolo Mantovani, Emilio Cota, Christian Pilato and Giuseppe Di Guglielmo authored a paper titled "An FPGA-Based Infrastructure for Fine-Grained DVFS Analysis in High-Performance Embedded Systems".

    Prof. Carloni presented an invited paper titled "The Case for Embedded Scalable Platforms".

    More information is available in this article on the Computer Science website.

  • Prof. Carloni's view on data centers accelerators makes the Tech Design Forum.

    An issue on the Tech Design Forum, "Minimize memory moves for greener data centers", reports Prof. Carloni's recommendations on memory systems and data movement for data center hardware accelerators. This article reviews current trends on heterogeneuos architectures memory management with a main focus on work from DAC 2016, where our group presented two papers.

  • Prof. Carloni guest editor of a Proceedings of the IEEE special issue on Electronic Design Automation

    Proceedings of the IEEE has released a special issue titled "Design Automation of Electronic Systems" on the evolution and future of Electronic Design Automation (EDA). Luca Carloni is one of four "word-leading guest editors" as mentioned in this article on the prweb news center.

  • Two SLD papers accepted to DAC'15

    Two papers coauthored by SLD members have been accepted to DAC'15.

    YoungHoon authored a paper titled "ΣVP: Host-GPU Multiplexing for Efficient Simulation of Multiple Embedded GPUs on Virtual Platforms".

    Emilio, Paolo and Giuseppe worked on a paper titled "An Analysis of Accelerator Coupling in Heterogeneous Architectures".

    The papers will be presented in June at DAC 2015 in San Francisco, CA.

    Congratulations to all of you!

  • Article published in special issue of Design & Test

    IEEE Design & Test recently published a special issue on Cloud Computing for Embedded Systems, putting together interesting articles, particularly including the one coauthored by SLD members.

    This special issue includes three papers, “The Swarm at the Edge of the Cloud”, “Middleware for IoT-Cloud Integration Across Application Domains”, and “Cloud-Aided Design for Distributed Embedded Systems”.

    The last article, presented by YoungHoon Jung, Michele Petracca, and Prof. Carloni, proposes a virtual execution platform for designing an embedded system using the cloud. Using this method, it is possible to emulate the interactions of millions of embedded systems that run various applications, such as image processing.

    The special issue is available on the IEEE Explorer.

  • Best Paper Award at DATE 2012

    Hung-Yi Liu and Michele Petracca, along with Prof. Carloni, have received the Best Paper Award for their work "Compositional System-Level Design Exploration with Planning of High-Level Synthesis", presented at the 2012 Design, Automation, and Test in Europe (DATE 2012) conference. It was the only best paper award assigned out of 950 submissions.


  • Three SLD papers accepted to DAC'13

    Three papers coauthored by SLD members have been accepted to DAC'13.

    Hung-Yi worked on two of these accepted submissions; he is the main author of "On Learning-Based Methods for Design-Space Exploration with High-Level Synthesis", and is the second author of "A Method to Abstract RTL IP Blocks into C++ Code and Enable High-Level Synthesis", whose first author is Nicola Bombieri. Nicola visited us last year from the University of Verona, where he is an Assistant Professor.

    YoungHoon is the main author of the third SLD accepted paper, titled "netShip: A Networked Virtual Platform for Large-Scale Heterogeneous Distributed Embedded Systems".

    The papers will be presented in June at DAC 2013 in Austin, TX.

    Congratulations to Hung-Yi and YoungHoon!

  • Best Paper Award at IEEE CloudCom

    YoungHoon Jung, Richard Neill and Luca Carloni have received the Best Paper Award for their work “A Broadband Embedded Computing System for MapReduce Utilizing Hadoop” presented at the 4th IEEE International Conference on Cloud Computing Technology and Science (CloudCom 2012) held in Taipei, Taiwan. The work was selected among the fifty-four papers accepted to the conference, which had a 17% acceptance rate.

  • Best in Session Award at SRC TECHCON 2012

    Young Jin Yoon received the Best in Session Award at the SRC TECHCON 2012 for the presentation and poster titled VENTTI: A Vertically Integrated Framework for Simulation and Validation of Networks-on-Chip. Congratulations!

  • Accelerator Memory Reuse in Computer Architecture Letters

    Our paper titled "Accelerator Memory Reuse in the Dark Silicon Era", which describes the reuse of accelerator memory as on-chip cache in the context of many-core architectures, has been accepted for publication and will soon be available as a Computer Architecture Letter.

  • In the Press: Business Wire cites SLD work

    Michele Petracca and Professor Carloni were cited by Business Wire for their work on embedded voltage regulators, developed in collaboration with Professor Ken Shepard’s group.

    Read more at Business Wire: Columbia University and Semiconductor Research Corporation Breathe New Life into Scalability by Integrating Voltage Regulators Directly onto ICs.

  • Hung-Yi's paper on Compositional System-Level Design Exploration accepted at DATE'12

    Congratulations to Hung-Yi for getting his paper, Compositional System-Level Design Exploration with Planning of High-Level Synthesis, accepted at the 2012 edition of the Design, Automation and Test Conference in Europe (DATE).

  • Best Student Demo Award at ACM SenSys 2011

    The demo titled Organic Solar Cell-equipped Energy Harvesting Active Networked Tag (EnHANT) Prototypes received the Best Student Demo Award at the ACM Conference on Embedded Networked Sensor Systems. The demo was developed by 10 students from several EE/CS groups at Columbia, with Marcin Sczcodrak representing SLD. Congratulations!

  • Prof. Carloni wins Investigator Award

    Luca Carloni received a three-year research grant as one of the recipients of the 2010 Young Investigator Program from the Office of Naval Research. The winning proposal is titled "Methods for System-level Design and Programming of Heterogeneous Embedded Multi-core Platforms". More information is available here.